Test methods and structures for semiconductor integrated circuits for electrically determining certain tolerances during the photolithographic steps

ABSTRACT

Test methods and structures are provided for electrically monitoring the image size tolerance (ΔW) during a critical photolithographic step in the processing of a semiconductor wafer. The test structure includes two symmetrical resistor bridges combined into a single structure exhibiting a specific topology and having specific nominal parameters of length and width. The structure further includes contact regions and contact voltages are respectively measured across the first and second bridges. The size tolerance is determined from the voltages. Therefore, the factor ΔW is directly determined by means of simple electrical measurements and, therefore, a data base is immediately provided with respect to the wafer in which the structure exists. Also, this invention relates to a method for monitoring the electrical tolerance (ΔA) where images are superimposed, which uses the preceding calculation.

TECHNICAL FIELD

This invention relates to the testing and monitoring of semiconductorwafers. More specifically, this invention relates to methods andstructures which are used for testing and monitoring and which allowcertain characteristics, such as the image size and overlay tolerances,to be determined during photolithographic steps.

BACKGROUND ART

It is known that, of the numerous processing steps involved in themanufacture of semiconductor integrated circuits (e.g. diffusion,epitaxial growth, metallurgy, etc.), the lithographic steps are the mostimportant, not only because they are frequently performed (some 10masking steps are required for a MOSFET, while approximately 15 are usedfor a bipolar transistor), but also because they ultimately determinethe density of the circuits. The efforts made to achieve an improveddensity have resulted in a significant development of lithographictechniques, which now involve electronbeam and x-ray exposures ratherthan the UV radiation exposures formerly used. Although finer and finerresolutions have thus been obtained (0.5 to 1 micron), the lithographicsteps have become more critical. It is well known that the maskinglayers (or the masks) used in the manufacture of integrated circuitsvary from the specifications established by the designer, as a result ofundesirable effects such as overexposure or underexposure of thephotoresist layers which may occur during fabrication of the maskinglayers or masks. Also, even if the width of the masking layer (or mask)is equivalent to the desired nominal width (W) of a line, anyoveretching or underetching of the insulating layer will result in thediffused regions being too wide or too narrow as compared with thenominal value. Lines exhibiting significant width variations (ΔW)relative to the nominal (design) value (W) can pose reliability problemsdue to short circuits or to open circuits and must therefore be detectedas early as possible during the manufacturing process.

Another important characteristic is that the diffused regions(resistors, lines, capacitors, etc.) formed through an insulating layeretched in accordance with a desired pattern and which may exhibitdimensional variations, can result in the components having incorrectratings and thus create problems during operation.

It is therefore important to correct misalignments and other defectsthat will cause a shift in the position of the image. These shifts areexpressed in terms of dimensional variations: instead of an etched areahaving a desired width W, there is obtained an etched area of which ΔW+W(ΔW being positive or negative). The relative tolerance is defined bythe ratio ΔW/W. Heretofore, this was determined visually, atime-consuming, costly process which did not yield meaningful databases.

Also, it is often useful to know the overlay tolerance applicable to acouple of superimposed images. Usually, this tolerance is measured andchecked visually, which entails the same disadvantages as thosementioned above.

SUMMARY OF THE INVENTION

A first object of the invention is to provide test methods andstructures that allow image size tolerances to be directly determined bymeans of essentially electrical measurements.

Another object of the invention is to replace the visual inspectionmethods, which are time-consuming, costly and not very reliable, by atest method that can easily be implemented automatically and whichpermits statistical data bases to be readily developed, which arecapable of yielding, if desired, wafer maps showing the good chips andthe bad ones.

Another object of the invention is to provide test structures and a testmethod which permit the photolithographic steps that are essential tothe manufacture of semiconductor devices and are often critical(particularly where small geometries are involved), to be monitored,both precisely and immediately, during the fabrication process.

Still another object of the invention is to provide test structures anda test method which, in combination with those already mentioned, allowthe overlay or the alignment tolerance associated with two superimposedimages to be determined by electric means.

Thus, the present invention relates to a test method and to teststructures that include two integrated resistor bridges formed in asemiconductor substrate, typically made of silicon and which, when acurrent is applied across a first diagonal, permit the potentialdifference across the other diagonal to be measured, the potentialdifferences associated with said bridges being designated ΔV1 and ΔV2,respectively. The sizes of the resistors are preferably selected so asto ensure that the dimensional tolerance will be a direct function ofthe measured voltages. Thus, in a preferred embodiment of the invention,the dimensional tolerance ΔW is related to the electrical values ΔV1 andΔV2 by means of an expression such as ##EQU1##

The subject invention also relates to the use of said test method andstructures, in relation to another structure comprised of an integratedresistor (or resistor bridge), for measuring overlay tolerances ΔA whentwo images are superimposed.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the topology of a first resistor bridge forming part of anintegrated structure formed in a silicon wafer for testing andmonitoring the size tolerance.

FIG. 2 shows the topology of a second resistor bridge constitutinganother part of the integrated structure formed in a silicon wafer fortesting and monitoring the size tolerance.

FIG. 3 depicts the topology of another test structure combining the tworesistor bridges mentioned above.

FIG. 4 shows the topology of a mask which is used for measuring theoverlay tolerance and exhibits two distinct configurations forperforming this measurement along two perpendicular axes.

FIG. 5 illustrates an integrated test structure formed in asemiconductor wafer for measuring the overlay tolerance when the twoconfigurations of FIG. 4 are superimposed.

DESCRIPTION OF THE INVENTION

The subject invention initially proposes two resistor bridges fordetermining the image size variations that are due to the numerouslithographic steps performed during the processing of semiconductorchips.

The size of the resistors is selected so as to ensure that the tolerancebeing determined will be a direct function of the voltages actuallymeasured.

FIG. 1 shows the topology of a first test structure consisting of afirst resistor bridge 10. This figure illustrates the configuration ofP-type resistors implanted or diffused in a N-type silicon substrate.

These resistors are formed by introducing impurities into a maskinglayer, typically SiO₂, in accordance with well-known techniques thatneed not be described here in detail. Alternatively, the illustratedresistors could have been deposited upon an insulating layer and etched.The resistors are made of a material exhibiting sufficient resistivityto allow the bridge unbalance to be measured, for examplepolycrystalline silicon or a metal. For simplicity, a symmetricalresistor bridge has been chosen.

The enlarged portions (or contact regions) that terminate the fourresistors include two regions 11a and 12a located on a first diagonal,which regions are generally aligned with the resistors R1 and R2 andprovided with contacts 11b and 12b consisting, for example, of aluminum.The illustrated contact configuration is preferred in order to ensurethat the direction of current flow will be generally parallel to theresistors R1 and R2, and to reduce the end resistance effects (R_(END)).A current I1 and the ground potential will respectively be applied tothese contacts. Two other regions, 13a and 14a, located on the seconddiagonal are also provided with contacts 13b and 14b, consisting, forexample, of aluminum, which will be used to measure the potentialdifference across this bridge.

The contact regions 13a and 14a are preferably aligned with the seconddiagonal to reduce undesirable end resistance effects. The configurationof these contact regions should preferably be as shown to facilitatepotential measurements (little current flows through the intermediateregions 13c and 14c). Accordingly, the test probes (not shown) should bepressed against the contacts 11b, 12, . . . , to apply or to measurecurrents or potentials.

The resistors R1 and R2 have different lengths designated L1 and L2,respectively, but have the same width W. For the purposes of thelithographic step, the width tolerance (or error, or variation) isexpressed as ΔW.

As is known, the masks used to form the desired resistive pattern on thesilicon wafer are generally comprised of a chromium layer deposited upona glass plate and a photo resist layer and involve the use ofconventional photolithographic techniques. Overexposure (orunderexposure) of the photoresist layer to light will cause line widthvariations in the mask pattern relative to the width specified by thecircuit designer. Also, overetching (or underetching) of the chromiumwill introduce additional variations. Finally, overetching (orunderetching) of the mask will introduce variations in the maskinglayer. These will ultimately add up to the overall error ΔW relative tothe nominal width W.

Knowing that the two branches of the bridge exhibit the same resistance,the following equations may be written:

    V.sub.A -V.sub.B =(I.sub.1 /2)(R2-R1)

Putting

    V.sub.A -V.sub.B =ΔV.sub.1

we get

    ΔV.sub.1 =(I.sub.1 /2)(R2-R1)                        (1)

We may also write ##EQU2## where ρ_(s) is the sheet resistance ofresistors R1 and R2: ΔL₁, ΔL₂ and ΔW are the tolerances with respect tolengths L1, L2 and to the width W (which is the same for bothresistors); and R_(END) is the end resistance between the resistor andthe contact. ΔL₁ is approximately equal to ΔL₂, at least as a firstapproximation.

Calculating R1-R2 and using Eq. (1), we find ##EQU3##

This relation fails to provide the desired ratio ΔW/W. To obtain thisratio, it is necessary to use a second test structure that is alsocomprised of a symmetrical resistor bridge 20, as shown in FIG. 2. Thetopology is fairly similar to that illustrated in FIG. 1. The structureincludes two enlarged portions or contact regions 21a, 22a located on afirst diagonal and provided with contacts 21b, 22b, made of aluminum,for example, to which a current I₂ and the ground potential arerespectively applied. These contact regions preferably include anintermediate portion 21c, 22c, exhibiting the configuration shown forreducing the effects of length and width variations as well as the endresistance effects. The potentials present in regions 23a and 24alocated on the other diagonal are similarly measured at terminals 23band 24b. Additional regions 25a and 26a may be arranged symmetricallywith regions 23a and 24a about the second diagonal in order to obtain abetter approximation of the potential difference ΔV₂ by calculating theaverage ##EQU4## We may also write

    ΔV.sub.2 =(I.sub.2 /2)(R'.sub.2 -R'.sub.1)           (3)

For simplicity, we will put W'1=W, L'₂ =L₂ and L'₁ =L₁.

Given this topology of the intermediate regions, we may assume thatthere is no error ΔL due to the etching operation and that the error ΔWis approximately equal to the error ΔW'₂, that is, ΔW'₂ ≈ΔW. Also, wemay write ##EQU5## and ##EQU6##

Calculating R'₂ -R'₁ and combining with Eq. (3), we find ##EQU7## Theabove relation may also be written, since (L₂)/(W'₂)=(L₁ /W) ##EQU8##and substituting ρ_(s) as given in Eq. (2), we get ##EQU9## whichsimplified to ##EQU10## If we put

    (I.sub.1 /I.sub.2)=K'

and if the designer requires that the following condition be satisified

    (L.sub.2 /L.sub.1)=(W'.sub.2 /W)=K                         (4)

we get ##EQU11## hence ##EQU12##

Thus, using the two test structures illustrated in FIGS. 1 and 2, theimage size tolerance (ΔW/W) can be derived from simple electricalmeasurements.

The circuit designer can also use preferred values for the parameters Kand K'. For example, if K'=1, i.e., I₁ =I₂, the two structures canreadily be combined to form a single structure 30 as shown in FIG. 3 (inwhich like reference numerals or characters designate like orcorresponding components identified in FIGS. 1 and 2). Lastly, we choseK=2, i.e. W'₂ =2W and L₂ =2L₁. Therefore, Eq. (5) becomes ##EQU13## with

    ΔV.sub.1 =V.sub.A -V.sub.B and ΔV.sub.2 =V.sub.A '-V.sub.B '

This measurement (ΔW/W), in addition to being useful in determining theimage tolerance (an important factor in evaluating the precision withwhich the etching process is performed), can serve to determine theimage overlay tolerances.

The parameters of the various resistors that make up the bridges havebeen selected in such a way as to simplify the calculations and topermit determining ΔW as a function of ΔV₁ and ΔV₂. It should, however,be noted that the principles of the invention remain applicable to anyother bridge structure, in which case ΔW would also be a function ofsaid parameters (L₁, W₁, . . . ).

FIG. 4 shows the topology of the mask corresponding to a test structurewhich allows the overlay tolerances to be electrically measured. Thistopology is characterized in that it includes a first Γ-shaped pattern41 comprised of two regions 41a and 41b and seven enlarged areas orcontact regions 42-48 that will enable electrical measurements to besubsequently taken. A mask registration region 40 is associated withthis first pattern. The mask includes a second pattern 50 comprised oftwo distinct, Γ-shaped regions 50a and 50b and another registrationregion 49. Region 50a will be aligned with region 41a but slightlyoffset relative thereto along the Y-axis when patterns 41 and 50 aresuperimposed and registration regions 40 and 49 aligned. Similarly,region 50b will be aligned with region 41b but slightly offset relativethereto along the X-axis. Thus, the two patterns are necessary only ifit is desired to determine the alignment tolerance along two axes. Thesilicon wafer, upon which an insulating layer (or a resistive layer madeof metal or polysilicon) and a photoresist layer have previously beendeposited, is successively exposed through patterns 41 and 50. This isdone by simply translating the mask. The translation takes place withinthe dimensional limits of the semiconductor chip so as to eliminate maskskew and positioning errors. If it is desired to include the tolerancesspecific to the mask in the measurement, then two separate maskscomprising patterns 50 and 41, respectively, must be used.

The photoresist layer is then etched away by conventional means. Thepattern finally obtained in the insulating layer corresponds to thesuperimposition of the two patterns. After an impurity has beenintroduced into the silicon substrate, a structure 52 is obtained whichis comprised of two resistors 52a and 52b as shown in solid lines inFIG. 5. If a resistive layer were used, these resistors would bedirectly obtained by etching the resistive layer. Resistors 52a and 52bwill serve to determine the alignment tolerances along the X-axis andthe Y-axis, respectively.

The width of the resistors is dependent upon the dimensional tolerancesassociated with patterns 41 and 50, and also on the misalignmentresulting from the superimposition of the two patterns. Thismisalignment is expressed as a so-called alignment or overlay toleranceΔA. When the image size tolerances are known, ΔA can be derived asfollows: the final width W' is dependent on the image size toleranceswith respect to patterns 41 (ΔW_(A)) and 50 (ΔW_(B)) and on thealignment tolerance (ΔA), in accordance with the relation ##EQU14## (ΔA,ΔW_(A) and ΔW_(B) may be positive or negative).

Now, the dimensional errors applicable to patterns 41 and 50 (ΔW_(A) andΔW_(B)) are provided by the test structures described in connection withFIGS. 1-3. It is apparent that the above computation is valid since thetest structures are adjacent on the silicon wafer, due to their beingformed either on a specialized chip (test site) or on the edge of thechip itself (kerf).

According to Eq. (6), we have

    ΔW.sub.A =m.sub.A W.sub.A and ΔW.sub.B =m.sub.B W.sub.B

W_(A) and W_(C) are very close to the widths specified by the circuitdesigner.

Accordingly, we find ##EQU15## and, if we set W_(A) +W_(C) =W_(D),##EQU16##

Using the metal contacts 46a, 47a provided on the enlarged regions 46,47, we can measure the value of the resistances

    R=ρ.sub.s (L)/(W'),

hence

    W'=ρ.sub.s (L/R)

and ##EQU17## where m_(A) and m_(B) characterize the dimensional errors,

ρ_(s) is the sheet resistance exhibited by the implanted or diffusedregion,

W_(A), W_(C) denote design widths, (hence W_(D))

L denotes a design length.

Thus, the alignment error can be immediately obtained through a simpleresistance measurement and an elementary calculation.

Lastly, to achieve a higher degree of precision, and assuming that thenumber of test points is not a limiting factor, the resistors 52a and52b may be replaced by resistor bridges which may be given differentorientations depending on whether the misalignment is measured along theX-axis or the Y-axis.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that numerous changes in form and detail may bemade therein without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A test structure formed in a semiconductor wafer,the wafer including semiconductor devices therein having lines made bylithographic process steps, the test structure formed in the wafer forelectrically monitoring the variations in line width relative to nominalline width (ΔW/W), the structure comprising:a first resistance bridgehaving a first branch including at least two resistive elements, eachelement having a resistance value defined by the length, width andresistivity of the element and a second branch including at least tworesistive elements, each element having a resistance value defined bythe length, width and resistivity of the element, the first branchelectrically connected in parallel with the second branch and of aresistance value approximately equal to that of the second branch, thefirst branch further including means for monitoring a voltage across oneresistive element in the first branch and the second branch furtherincluding means for monitoring voltage across one resistive element inthe second branch so that when a current is applied to the bridge, avoltage difference (ΔV₁) between the two branches can be measured, and asecond resistive bridge having a first branch including at least tworesistive elements, each element having a resistance value defined bythe length, width and resistivity of the element and a second branchincluding at least two resistive elements, each element having aresistance value defined by the length, width and resistivity of theelement, the first branch electrically connected and parallel with thesecond branch and of a resistance value approximately equal to thesecond branch, the first branch including means for monitoring a voltageat one resistive element of the first branch and means for monitoringthe voltage at one resistive element of the second branch so that thevoltage difference between the two elements (ΔV₂) can be monitored whena current is applied to the second bridge whereby variation in linewidth relative to nominal line width (ΔW/W) for lines fabricated in andon the wafer may be directly monitored by measuring the voltagedifference (ΔV₁) between the first and second branches of the firstbridge and the voltage difference (ΔV₂) between the first and secondbranches of the second bridge.
 2. The test structure of claim 1 whereinthe first bridge is electrically connected in series with the secondbridge.
 3. The test structure of claim 2 wherein the width of thevoltage monitored resistive elements of the first branch of the firstand second bridges respectively are equal to the respective width of thevoltage monitored elements of the second branch of the first and secondbridges, but wherein the lengths of the voltage monitored resistiveelements of the first branch of the first and second bridge respectivelyare not equal to the respective lengths of the voltage monitoredresistive element of the second branch of the first and second bridges.4. The test structure of claim 2 wherein the width of the voltagemonitored resistive element of the first branch of the first bridge isequal to the width of the voltage monitored element of the second branchof the first bridge and equal to the width of the voltage monitoredelement of the first branch of the second bridge, but where the width ofthe voltage monitored element of the second branch of the second bridgeis equal to twice the width of the voltage monitored element of thefirst branch of the second bridge and where the length of the voltagemonitored element of the first branch of the first bridge is equal tothe length of the voltage monitored element of the first branch of thesecond bridge and the length of the voltage monitored element of thesecond branch of the first bridge is equal to the length of the voltagemonitored element of the second branch of the second bridge which itselfis equal to twice the length of the voltage monitored element of thefirst branch of the second bridge and where the current supplied to thefirst bridge and the second bridge is equal so that the variation ofline width relative to nominal line width (ΔW/W) is determined bymonitoring the voltage measured at the first bridge (ΔV₁) and the secondbridge (ΔV₂) according to the following relationship: ##EQU18##
 5. Thetest structure of claim 3 or 4 wherein the first and second bridges areprovided with contact regions for making electrical connections whichminimize end resistance effects.
 6. A structure according to claim 5,wherein the test structure is located either on the periphery of thechip (Kerf) or in a specialized chip (test site).